1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, relates to a multi-bank semiconductor memory device having a plurality of banks which can be driven into an active/inactive state independently of each other. The invention more specifically relates to a structure for bank control of a synchronous semiconductor memory device which operates in synchronization with a clock signal.
2. Description of the Background Art
A synchronous semiconductor memory device having data input/output synchronously with a clock signal has been known. In the synchronous semiconductor memory device, a clock signal determines the data input/output rate, and data can be transferred according to a high speed clock signal which is a system clock, for example. As a result, necessary data can be provided to a processor operating at a high speed in a short time. The waiting time of the processor is thus reduced and the performance of a processing system is improved.
One such synchronous semiconductor memory device is a synchronous dynamic random access memory (SDRAM). The SDRAM includes a dynamic memory cell of one transistor/one capacitor type as a memory cell. In SDRAM, external signals or a control signal and an address signal as well as write data are taken into the device at, for example, a rising edge of a clock signal, and read data attains a defined state at the rising edge of the clock signal. In the SDRAM, an instruction on an operation mode is supplied as a combination of logic states of a plurality of external control signals. The operation mode instruction is generally referred to as "command". By giving an instruction as to an operation mode in the form of a command, an operation mode instruction can be given every clock cycle, so that a plurality of memory arrays can be internally driven independently of each other. A plurality of banks are generally provided internally in the SDRAM. Concerning 16 M-bit SDRAM, for example, a specification according to which 2 banks are internally provided is standardized by JEDEC (Joint Electron Device Engineering Council).
FIG. 25 shows states of external signals at the time of data reading in a conventional SDRAM.
In clock cycle #0, an external row address strobe signal ZRAS is set to an L level and a column address strobe signal ZCAS and a write enable signal ZWE are set to an H level at a rising edge of an external clock signal extCLK. The state of the signals referred to as an active command designates array activation. "Array activation" is an operation of driving a row in a memory cell array into a selected state and carrying out detection, amplification, and latching for data in a memory cell connected to the selected row by a sense amplifier. When the active command is issued, a row selecting operation is carried out for a bank designated by a bank address signal BA using an address signal ADD concurrently applied as a row address signal X. With two bank structure, bank address signal BA is an 1-bit signal, and bank address signal BA is set to the H level to designate a bank #A in the clock cycle #0. Accordingly, the bank #A is driven into an active state.
In a clock cycle #1, at a rising edge of external clock signal extCLK, row address strobe signal ZRAS and write enable signal ZWE are set to the H level and column address strobe signal ZCAS is set to the L level. This state referred to as a read command designates reading of data. When the read command is given, a column selecting operation is carried out for the bank #A designated by the current bank address signal BA, using address signal ADD concurrently applied as a column address signal, and data in a selected memory cell is read.
A clock cycle period required from the supply of read command to output of valid data in the SDRAM is referred to as CAS latency. Valid data is output when the CAS latency has passed. In FIG. 25, a data reading operation with the CAS latency of 2 is represented. In this case, data in a memory cell addressed by a column address signal Y in the bank #A attains a defined state at a rising edge of clock signal extCLK in a clock cycle #3 (shown as data a0).
In the SDRAM, a column address signal is internally generated according to a prescribed sequence with an address signal at the time of the supply of the read command as a leading address, and a selecting operation for a memory cell is successively carried out according to the internally generated column address signal (burst address signal). Accordingly, data a1, a2, and a3 are successively read from the bank #A in clock cycles #4, #5 and #6.
In parallel with reading of data from bank #A, an active command is supplied in clock cycle #4. At this time, bank address signal BA is set to the L level to designate another bank #B. As a result, in clock cycle #4, bank #B is activated, current address signal ADD is used as a row address signal X, and a row selecting operation is carried out.
In clock cycle #5, bank #B is designated by setting bank address signal BA to the L level again, and a read command is issued. The read command allows a column selecting operation to be carried out for bank #B, and data in a memory cell on a selected column is read out.
As the CAS latency is 2, data is read out in bank #B in clock cycle #6, and memory cell data b0 from bank #B attains a defined state at a rising edge of an external clock signal extCLK in clock cycle #7. A burst address signal is also internally generated in bank #B, memory cells are successively selected and data in a selected memory cell is read. The number of data read out successively when one read command is supplied is referred to as a burst length. FIG. 25 represents a data reading operation when the burst length is 4.
On the other hand, row address strobe signal ZRAS and write enable signal ZWE are set to the L level and column address strobe signal ZCAS is set to the H level to supply a precharge command in clock cycle #6. The precharge command is a command which drives a bank in an active state to an inactive state. The precharge command allows a bank addressed according to bank address signal BA to be precharged. Therefore, bank address signal BA is at the H level at a rising edge of external clock signal extCLK in clock cycle #6, bank #A is designated, and bank #A is inactivated.
In parallel with a reading operation for data b1, b2 and b3 from bank #B, in clock cycle #8, bank address signal BA is set to the H level again to supply an active command to bank #A. Bank #A is thus activated again. Next in clock cycle #9, a read command is supplied for bank #A. Data from bank #A is read after reading of the last data b3 of the burst length data from bank #B (shown as (a) in FIG. 25).
When two banks are provided as described above, the banks are alternately activated/inactivated. Even if different rows (word lines) are accessed, the RAS precharge time in a standard DRAM is unnecessary to achieve a high speed data reading.
FIG. 26 is a timing chart showing states of external signals at the time of data writing. Referring to FIG. 26, a data reading operation is described. FIG. 26 shows an operation sequence when two banks are provided and data are alternately written into the banks with the burst length of 4.
In clock cycle #0, bank address signal BA is set to the H level and an active command is issued. Bank #A is thus activated and a row selecting operation is carried out using a concurrently applied address signal ADD as row address signal X.
At a rising edge of external clock signal extCLK in clock cycle #1, row address strobe signal ZRAS is set to The H level, column address strobe signal ZCAS and write enable signal ZWE are set to the L level, and a write command is given. Bank address signal BA supplied at the same time as the write command is set to the H level, and an instruction of data writing into bank #A is given. When the write command is supplied, a column selection is carried out using the concurrently applied address signal ADD as a column address signal, and data writing is performed.
When data is written, data applied in a clock cycle in which a write command is supplied is taken into the SDRAM to perform the writing. In other words, data c0 supplied in clock cycle #1 is taken into the memory device. Column address signals are generated internally according to a prescribed sequence with address signal ADD supplied in clock cycle #1 in bank #A as a leading address, as when data is read out. In clock cycles #2, #3 and #4, column selecting operations are respectively carried out, and data c1, c2 and c3 supplied currently are successively written into selected memory cells in a prescribed sequence.
In parallel with the data writing operation for bank #A, in clock cycle #4, bank address signal BA is set to the L level and an active command is supplied. In this case, an instruction of activation of bank #B is supplied, and a row in a memory cell is selected using address signal ADD currently applied as row address signal X in bank #B. In the next clock cycle #5, bank address signal BA is set to the L level again and a write command is given. Accordingly, data b0 supplied in clock cycle #5 is taken into the SDRAM, and a data writing operation for bank #B is carried out. Burst address signals are thereafter internally generated according to a prescribed sequence in bank #B and a column selecting operation is internally performed. Data d1, d2 and d3 respectively supplied in clock cycles #6, #7 and #8 are taken into the memory device, and data is written into selected memory cells according to a prescribed sequence.
In parallel with the data writing operation for bank #B, in clock cycle #6, bank address signal BA is set to the H level and a precharge command is supplied. Bank #A is thus inactivated and a memory cell array returns to a precharge state.
In clock cycle #8, bank address signal BA is set to the H level again to supply active command. Bank #A in the inactive state is again activated and a memory cell row is selected. Next in clock cycle #9, bank address signal BA is set to the H level and a write command for bank #A is issued. From clock cycle #9, data writing for bank #A is carried out. After that, data c4, c5 . . . are written into selected memory cells in bank #A according to a prescribed sequence.
When data is written as above, banks #A and #B are alternately activated/inactivated and data are written. As a result, the RAS precharge time (a time required from returning of a memory cell array to the precharge state to driving thereof into the active state again) which is necessary for returning a selected or activated memory cell array to the precharge state at the time of the page switching never affects an external access. Data can be successively written in each clock cycle and a high speed data writing is achieved.
FIG. 27 shows a structure of a main portion of the conventional SDRAM. Referring to FIG. 27, the conventional SDRAM includes: a bank address input buffer 1 which takes in an externally supplied bank address signal BA at a rising edge of internal clock signal CLK generated synchronously with external clock signal extCLK and generates internal bank address signals BAi and /BAi that are complimentary to each other; a command decoder 2 which incorporates externally supplied control signals ZRAS, ZCAS and ZWE at a rising edge of internal clock signal CLK, determines the states of those signals and generates an operation mode instruction signal .phi. according to the result of the determination; and a bank control circuit 3 which outputs an operation mode designation signal for bank #A and bank #B according to operation mode instruction signal .phi. supplied from command decoder 2 as well as internal bank address signals BAi and /BAi supplied from bank address input buffer 1. Although operation mode instruction signals from command decoder 2 are generated corresponding to respective commands shown in FIG. 25 and 26, one signal .phi. represents the signals in FIG. 27.
Bank control circuit 3 includes an AND circuit 3a receiving internal bank address signal BAi and operation mode instruction signal .phi., and an AND circuit 3b receiving internal bank address signal /BAi and operation mode instruction signal .phi.. Operation mode instruction signal .phi.A is output for bank #A from AND circuit 3a, and operation mode instruction signal .phi.B is output for bank #B from AND circuit 3b.
One of internal bank address signals BAi and /BAi generated by bank address input buffer 1 is at the H level, and the other is at the L level. As a result, an operation mode designation signal according to an operation mode instruction signal from command decoder 2 is output for only a bank designated by bank address signal BA, the operation mode instruction signal for the addressed bank attains an active state (H level), and the designated operation is carried out.
As shown in FIG. 27, if a command is supplied to SDRAM, bank address signal BA designating a bank for which an operation is carried out should be supplied. The reason is that an operation mode for a bank in the active state should be designated without fail since there is a case in which two banks are simultaneously being activated.
However, there is a case in which a high-speed access in such a bank interleave manner is not required but an access is made by always activating only one bank. In the field of the image processing, for example, if a memory device is structured such that pixel data on even fields are stored in one of two banks and pixel data on odd fields are stored in the other bank, only one bank is accessed during one field period so that one bank is successively accessed. In this case, if a bank to be activated according to a bank address signal is designated when an active command is given, an operation mode instruction is issued for the activated bank and a bank is not particularly required to be designated using a bank address signal when the read command, write command and precharge command are supplied. However, in the conventional SDRAM, once a bank is activated, an operation mode instruction for the bank should be thereafter issued concurrently with a bank address signal. In this case, the bank address signal would be unnecessarily driven, the electric power for driving the bank address signal is unnecessarily consumed, and the consumed power of the entire system cannot be decreased. Further, even if the banks are not simultaneously being activated, a bank address signal has to be supplied with a command. Even. if a bank in which some operation is carried out is apparent, an external controller should supply a bank address signal, resulting in increase of the load of the external controller.